As an AI Accelerator Front-End RTL Designer, you will develop high-performance SoC architectures integrating advanced memory technology, NPU, CPU, and NoC IPs. Responsibilities include designing memory controllers, Verilog RTL implementation, and leading synthesis, timing closure, and power optimization activities.
Location: Grenoble / Hybrid
Vertical Compute
HQ: Louvain-la-Neuve, Belgium
Founded: 2024
Team Size: 21–50